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PF926-02
SED1565 Series SED1565 Series
Dot Matrix LCD Driver SSC5000Series
s DESCRIPTION
The SED1565 Series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the microprocessor. Because the chips in the SED1565 Series contain 65 x 132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The SED1565 Series chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65 x 132 dot display (capable of displaying 8 columns x 4 rows of a 16 x 16 dot kanji font). The SED1567 Series chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 x 132 dot display (capable of displaying 8 columns x 2 rows of 16 x 16 dot kanji fonts). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the SED1565 Series chips can be used to create the lowest power display system with the fewest components for high-performance portable devices.
s FEATURES
q Direct display of RAM data through the display data RAM. RAM bit data: "1" Non-illuminated "0" Illuminated (during normal display) q RAM capacity 65 x 132 = 8580 bits q Display driver circuits SED1565***: 65 common output and 132 segment outputs SED1566***: 49 common output and 132 segment outputs SED1567***: 33 common outputs and 132 segment outputs SED1568***: 55 common outputs and 132 segment outputs SED1569***: 53 common outputs and 132 segment outputs q High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported. q Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. q Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) q Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of Double/Triple/ Quad, where the step-up voltage reference power supply can be input externally) High-accuracy voltage adjustment circuit (Thermal gradient -0.05%/C or -0.2%/C or external input) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. q CR oscillator circuit equipped internally (external clock can also be input)
1
SED1565 Series
q Extremely low power consumption Operating power when the built-in power supply is used (an example) SED1565D0B 81 A (VDD - VSS = VDD - VSS2 = /SED1565DBB 3.0 V, Quad voltage, V5 - VDD = -11.0 V) SED1566D0B 43 A (VDD - VSS = VDD - VSS2 = /SED1566DBB 3.0 V, Triple voltage, V5 - VDD = -8.0 V) SED1567D0B 29 A (VDD - VSS = VDD - VSS2 = /SED1567DBB 3.0 V, Triple voltage, V5 - VDD = -8.0 V) SED1568D0B 46 A (VDD - VSS = VDD - VSS2 = /SED1568DBB 3.0 V, Triple voltage, V5 - VDD = /SED1569D0B -8.0 V) /SED1569DBB Conditions: When all displays are in white and the normal mode is selected. q Power supply Operable on the low 1.8 voltage Logic power supply VDD - VSS = 1.8 V to -5.5 V Boost reference voltage: VDD - VSS2 = 1.8 V to -6.0 V Liquid crystal drive power supply: VDD - V5 = -4.5 V to -16.0 V q Wide range of operating temperatures: -40 to 85C q CMOS process q Shipping forms include bare chip and TCP. q These chips not designed for resistance to light or resistance to radiation.
s SERIES SPECIFICATIONS
Product Name Duty Bias SED Dr COM Dr VREG Temperature Gradient Shipping Forms Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip TCP Bare Chip Bare Chip TCP
SED1565D0B 1/65 1/9, 1/7 132 65 -0.05%/C /SED1565DBB SED1565T0* 1/65 1/9, 1/7 132 65 -0.05%/C 1/65 1/9, 1/7 132 65 -0.2%/C * SED1565D1B 1/65 1/9, 1/7 132 65 -0.2%/C * SED1565T1* 1/65 1/9, 1/7 132 65 External Input SED1565D2B SED1565T2* 1/65 1/9, 1/7 132 65 External Input SED1566D0B 1/49 1/8, 1/6 132 49 -0.05%/C /SED1566DBB SED1566T0* 1/49 1/8, 1/6 132 49 -0.05%/C 1/49 1/8, 1/6 132 49 -0.2%/C SED1566D1B 1/49 1/8, 1/6 132 49 -0.2%/C * SED1566T1* 1/49 1/8, 1/6 132 49 External Input SED1566D2B * SED1566T2* 1/49 1/8, 1/6 132 49 External Input SED1567D0B 1/33 1/6, 1/5 132 33 -0.05%/C /SED1567DBB SED1567T0* 1/33 1/6, 1/5 132 33 -0.05%/C 1/33 1/6, 1/5 132 33 -0.2%/C SED1567D1B 1/33 1/6, 1/5 132 33 -0.2%/C * SED1567T1* SED1567D2B 1/33 1/6, 1/5 132 33 External Input * SED1567T2* 1/33 1/6, 1/5 132 33 External Input SED1568D0B 1/55 1/8, 1/6 132 55 -0.05%/C /SED1568DBB SED1569D0B 1/53 1/8, 1/6 132 53 -0.05%/C /SED1569DBB SED1569T0* 1/53 1/8, 1/6 132 53 -0.05%/C Note: The circuit for the VREG temperature gradient -0.2%/C and the external input is under preparation. * : Under development
2
SED1565 Series
s BLOCK DIAGRAM
Example: SED1565***
SEG131 COM63 Display timing generation circuit
*************************
**********
VSS VDD V1 V2 V3 V4 V5 COM output status select circuit CAP1+ CAP1- CAP2+ CAP2- CAP3+ VOUT Power supply circuit Display data latch circuit SEG Drivers COM Drivers
COMS
COMS
COM0
SEG0
Page address circuit
Line address circuit
FRS FR CL DOF M/S
I/O buffer
Display data RAM 132 x 65
VSS2 VR VRS IRS HPM
Column address circuit
Oscillator circuit
CLS
Bus holder
Command decoder
Status
MPU interface
D6 (SCL)
WR (R/W)
D7 (SI)
RD (E)
RES
CS1
CS2
P/S
D5
D4
D3
D2
D1
D0
A0
3
SED1565 Series
s PAD LAYOUT
Chip Size Bump Pitch Bump Size
Bump Height
10.82 mm x 2.81 mm 71 m (Min.) PAD #1~24 PAD #25~82 PAD #83~99 PAD #100 PAD #101~133 PAD #134 PAD #135 PAD #136~273 PAD #274 PAD #275 PAD #276~308 PAD #309 17 m (Typ.)
85 m x 85 m 64 m x 85 m 85 m x 85 m 85 m x 73 m 85 m x 47 m 85 m x 73 m 73 m x 85 m 47 m x 85 m 73 m x 85 m 86 m x 73 m 85 m x 47 m 85 m x 73 m
4
SED1565 Series
s PIN DESCRIPTIONS
q Power Supply Pins
Pin Name VDD VSS VSS2 VRS I/O Power Supply Power Supply Power Supply Power Supply Power Supply Function Shared with the MPU power supply terminal VCC. This is a 0 V terminal connected to the system GND. This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. This is the externally-input VREG power supply for the LCD power supply voltage regulator. These are only enabled for the models with the VREG external input option. This is a multi-level power supply for the liquid crystal drive. The voltage applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. VDD (= V0) V1 V2 V3 V4 V5 Master operation: When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. SED1565*** 1/9 * V5 1/7 * V5 2/9 * V5 2/7 * V5 7/9 * V5 5/7 * V5 8/9 * V5 6/7 * V5 SED1566*** 1/8 * V5 1/6 * V5 2/8 * V5 2/6 * V5 6/8 * V5 4/6 * V5 7/6 * V5 5/6 * V5 SED1567*** 1/6 * V5 1/5 * V5 2/6 * V5 2/5 * V5 4/6 * V5 3/5 * V5 5/6 * V5 4/5 * V5 SED1569*** 1/8 * V5 1/6 * V5 2/8 * V5 2/6 * V5 6/8 * V5 4/6 * V5 7/8 * V5 5/6 * V5 # of Pins 13 9 4 2
V1, V2, V3, V4, V5
10
V1 V2 V3 V4
q LCD Power Supply Circuit Pins
Pin Name CAP1+ CAP1- CAP2+ CAP2- CAP3- VOUT VR I/O O O O O O O I Function DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. These are only enabled when the V5 voltage regulator internal resistors are not used (IRS = "L"). These cannot be used when the V5 voltage regulator internal resistors are used (IRS = "H"). # of Pins 2 2 2 2 2 2 2
5
SED1565 Series
q System Bus Connection Terminals
Pin Name D7 to D0 (SI) (SCL) I/O I/O Function This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = "L"), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = "H": Indicates that D0 to D7 are display data. A0 = "L": Indicates that D0 to D7 are control data. When RES is set to "L," the settings are initialized. The reset operation is performed by the RES signal level. This is the chip select signal. When CS1 = "L" and CS2 = "H," then the chip select becomes active, and data/command I/O is enabled. * When connected to an 8080 MPU, this is active LOW. This pin is connected to the RD signal of the 8080 MPU, and the SED1565 series data bus is in an output status when this signal is "L". * When connected to a 6800 Series MPU, this is active HIGH. This is the 68000 Series MPU enable clock input terminal. * When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. * When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = "H": Read. When R/W = "L": Write. This is the MPU interface switch terminal. C86 = "H": 6800 Series MPU interface. C86 = "L": 8080 MPU interface. This is the parallel data input/serial data input switch terminal. P/S = "H": Parallel data input. P/S = "L": Serial data input. The following applies depending on the P/S status: P/S "H" "L" Data/Command A0 A0 Data D0 to D7 SI (D7) Read/Write RD, WR Write only Serial Clock SCL (D6) # of Pins 8
A0
I
1
RES CS1 CS2 RD (E)
I I I
1 2 1
WR (R/W)
I
1
C86
I
1
P/S
I
1
CLS
I
When P/S = "L", D0 to D5 are HZ. D0 to D5 may be "H", "L" or Open. RD (E) and WR (P/W) are fixed to either "H" or "L". With serial data input, RAM display data reading is not supported. Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = "H": Internal oscillator circuit is enabled CLS = "L": Internal oscillator circuit is disabled (requires external input) When CLS = "L", input the display clock through the CL terminal.
1
6
SED1565 Series
Pin Name M/S I/O I Function This terminal selects the master/slave operation for the SED1565 Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. M/S = "H": Master operation M/S = "L": Slave operation The following is true depending on the M/S and CLS status: M/S "H" "L" CLS "H" "L" "H" "L" Oscillator Circuit Enabled Disabled Disabled Disabled Power Supply Circuit Enabled Enabled Disabled Disabled CL Output Input Input Input FR Output Output Input Input FRS Output Output Output Output DOF Output Output Input Input 1 # of Pins 1
CL
I/O
This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S "H" "L" CLS "H" "L" "H" "L" CL Output Input Input Input
FR
I/O
DOF
I/O
FRS
O
IRS
I
HPM
I
When the SED1565 Series chips are used in master/slave mode, the various CL terminals must be connected. This is the liquid crystal alternating current signal I/O terminal. M/S = "H": Output M/S = "L": Input When the SED1565 Series chip is used in master/slave mode, the various FR terminals must be connected. This is the liquid crystal display blanking control terminal. M/S = "H": Output M/S = "L": Input When the SED1565 Series chip is used in master/slave mode, the various DOF terminals must be connected. This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON when in master operation mode, and is used in conjunction with the FR terminal. This terminal selects the resistors for the V5 voltage level adjustment. IRS = "H": Use the internal resistors IRS = "L": Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either "H" or "L" when the slave operation mode is selected. This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = "H": Normal mode HPM = "L": High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either "H" or "L" when the slave operation mode is selected.
1
1
1
1
1
7
SED1565 Series
q Liquid Crystal Drive Pins
Pin Name SEG0 to SEG131 I/O O Function These are the liquid crystal segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5. RAM DATA H H L L Power save COM0 to COM31 O FR H L H L -- Output Voltage Normal Display Reverse Display VDD V2 V5 V3 V2 VDD V3 V5 VDD # of Pins 132
These are the liquid crystal common drive outputs. Part No. SED1565*** SED1566*** SED1567*** SED1568*** SED1569*** COM COM 0 to COM 63 COM 0 to COM 47 COM 0 to COM 31 COM 0 to COM 53 COM 0 to COM 51 Part No. SED1565*** SED1566*** SED1567*** SED1568*** SED1569*** 64 48 32 54 52 64
Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V1, V4, and V5. Scan Data H H L L Power Save COMS O FR H L H L -- Output Voltage V5 VDD V1 V4 VDD
These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. When in master/slave mode, the same signal is output by both master and slave.
2
q Test Terminals
Pin Name TEST0 to 9 I/O I/O These are terminals for IC chip testing. They are set to OPEN. Function No. of Pins 14 Total: 288 pins for the SED1565***. 272 pins for the SED1566***. 256 pins for the SED1567***. 276 pins for the SED1569***.
8
SED1565 Series
s ABSOLUTE MAXIMUM RATINGS
Unless otherwise noted, VSS = 0 V
Parameter Power Supply Voltage Power supply voltage (2) (VDD standard) With Triple step-up With Quad step-up Power supply voltage (3) (VDD standard) Power supply voltage (4) (VDD standard) Input voltage Output voltage Operating temperature Storage temperature TCP Bare chip Symbol VDD VSS2 Conditions -0.3 to +7.0 -7.0 to +0.3 -6.0 to +0.3 -4.5 to +0.3 -18.0 to +0.3 V5 to +0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -40 to +85 -55 to +100 -55 to +125 Unit V V
V5, VOUT V1, V2, V3, V4 VIN VO TOPR TSTR
V V V V C C
VCC GND
VDD VSS
VDD
VSS2, V1 to V4
V5, VOUT System (MPU) side SED1565 Series chip side
Notes and Cautions 1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD V1 V2 V3 V4 V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.
9
SED1565 Series
s DC CHARACTERISTICS
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V 10%, Ta = -40 to 85C
Item Recommended Voltage Possible Operating Voltage Operating Recommended Voltage (2) Voltage Possible Operating Voltage Operating Possible Voltage (3) Operating Voltage Possible Operating Voltage Possible Operating Voltage High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Static Consumption Current Output Leakage Current Input Terminal Capacitance Oscillator Internal Frequency Oscillator External Input Internal Oscillator External Input Input voltage Supply Step-up output voltage Circuit Voltage regulator Circuit Operating Voltage Voltage Follower Circuit Operating Voltage Base Voltage Operating Voltage (1) Symbol VDD Condition Min. 2.7 1.8 Rating Typ. -- -- Max. 3.3 5.5 Units V V Applicable Pin VDD*1 VDD*1
VSS2 VSS2
(Relative to VDD) (Relative to VDD)
-3.3 -6.0
-- --
-2.7 -1.8
V V
VSS2 VSS2
V5 V1, V2 V3, V4
(Relative to VDD) (Relative to VDD) (Relative to VDD)
-16.0 0.4 x V5 V5
-- -- --
-4.5 VDD 0.6 x V5
V V V
V5 *2 V1, V2 V3, V4
VIHC VILC VOHC VOLC ILI ILO RON ISSQ I5Q CIN fOSC fCL fOSC fCL VSS2 VSS2 VOUT VOUT V5 VREG0 VREG1
0.8 x VDD -- VDD V VSS -- 0.2 x VDD V IOH = -0.5 mA 0.8 x VDD -- VDD V IOL = 0.5 mA VSS -- 0.2 x VDD V VIN = VDD or VSS -1.0 -- 1.0 A -3.0 -- 3.0 A Ta = 25C V5 = -14.0 V -- 2.0 3.5 K (Relative To VDD) V5 = -8.0 V -- 3.2 5.4 K -- 0.01 5 A V5 = -18.0 V (Relative To VDD) -- 0.01 15 A Ta = 25C f = 1 MHz -- 5.0 8.0 pF Ta = 25C 18 22 26 kHz SED1565 **/1567 ** * * Ta = 25C SED1566 **/1569 ** * * With Triple (Relative To VDD) With Quad (Relative To VDD) (Relative to VDD) (Relative to VDD) (Relative to VDD) Ta = 25C (Relative to VDD) -0.05%/C -0.2%/C 18 27 14 -6.0 -4.5 -18.0 -18.0 -16.0 -2.16 -5.15 22 33 17 -- -- -- -- -- -2.10 -4.9 26 39 20 -1.8 -1.8 -- -6.0 -4.5 -2.04 -4.65 kHz kHz kHz V V V V V V V
*3 *3 *4 *4 *5 *6 SEGn COMn *7 VSS, VSS2 V5 *8 CL *8 CL VSS2 VSS2 VOUT VOUT V5 *9 *10 *10
10
Internal Power
SED1565 Series
* Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. Display Pattern OFF
Item SED1565 ** * SED1566 ** * Symbol IDD (1) Condition VDD = 5.0 V, V5 - VDD = -11.0 V VDD = 3.0 V, V5 - VDD = -11.0 V VDD = 3.0 V, V5 - VDD = -11.0 V VDD = 5.0 V, V5 - VDD = -8.0 V VDD = 3.0 V, V5 - VDD = -8.0 V VDD = 5.0 V, V5 - VDD = -8.0 V VDD = 3.0 V, V5 - VDD = -8.0 V VDD = 5.0 V, V5 - VDD = -8.0 V VDD = 3.0 V, V5 - VDD = -8.0 V Min. -- -- -- -- -- -- -- -- -- Rating Typ. 18 16 13 11 9 8 7 12 10 Max. 30 27 22 19 15 13 12 20 17 Ta = 25C Units A Notes *11
SED1567 ** * SED1568 **/SED1569 ** * *
Display Pattern Checker
Item SED1565 ** * SED1566 ** * Symbol IDD (1) Condition VDD = 5.0 V, V5 - VDD = -11.0 V VDD = 3.0 V, V5 - VDD = -11.0 V VDD = 3.0 V, V5 - VDD = -11.0 V VDD = 5.0 V, V5 - VDD = -8.0 V VDD = 3.0 V, V5 - VDD = -8.0 V VDD = 5.0 V, V5 - VDD = -8.0 V VDD = 3.0 V, V5 - VDD = -8.0 V VDD = 5.0 V, V5 - VDD = -8.0 V VDD = 3.0 V, V5 - VDD = -8.0 V Min. -- -- -- -- -- -- -- -- -- Rating Typ. 23 21 17 14 12 11 10 15 13 Max. 38 35 29 24 20 18 17 25 22
Ta = 25C Units A Notes *11
SED1567 ** * SED1568 **/SED1569 ** * *
* Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON Display Pattern OFF
Item SED1565 ** * Symbol IDD (2) Condition VDD = 5.0 V, Triple step-up voltage. V5 - VDD = -11.0 V VDD = 3.0 V, Quad step-up voltage. V5 - VDD = -11.0 V SED1566 ** * VDD = 5.0 V, Double step-up voltage. V5 - VDD = -8.0 V VDD = 3.0 V, Triple step-up voltage. V5 - VDD = -8.0 V VDD = 3.0 V, Quad step-up voltage. V5 - VDD = -11.0 V SED1567 ** * VDD = 5.0 V, Double step-up voltage. V5 - VDD = -8.0 V VDD = 3.0 V, Triple step-up voltage. V5 - VDD = -8.0 V SED1568 ** / * SED1569 ** VDD = 5.0 V, Double step-up voltage. V5 - VDD = -8.0 V VDD = 3.0 V, Triple step-up voltage. V5 - VDD = -8.0 V Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Normal Mode High-Power Mode Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rating Typ. 67 114 81 138 35 64 43 84 72 128 26 60 29 73 37 67 46 87 Max. 112 190 135 230 59 107 72 140 121 214 44 100 49 122 62 112 77 145
Ta = 25C Units Notes A *12
*
11
SED1565 Series
s TIMING CHARACTERISTICS
q System Bus Read/Write Characteristics 1 (for the 8080 Series MPU)
A0
tAW8
CS1 (CS2="1")
tAH8
tCYC8 tCCLR, tCCLW
WR, RD
tCCHR, tCCHW tDS8
D0 to D7 (Write)
tDS8
tACC8
D0 to D7 (Read)
tOH8
Item Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Address hold time RD access time Output disable time
Signal A0 A0 WR RD WR RD D0 to D7
Symbol
Condition -- -- --
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8
-- CL = 100 pF
(VDD = 4.5 V to 5.5 V, Ta = -40 to 85C ) Rating Units Min Max 0 -- ns 0 -- ns 166 -- ns 30 -- ns 70 -- ns 30 -- ns 30 -- ns 30 -- ns 10 -- ns -- 70 ns 5 50 ns (VDD = 2.7 V to 4.5 V, Ta = -40 to 85C ) Rating Units Min Max 0 -- ns 0 -- ns 300 -- ns 60 -- ns 120 -- ns 60 -- ns 60 -- ns 40 -- ns 15 -- ns -- 140 ns 10 100 ns
Item Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Address hold time RD access time Output disable time
Signal A0 A0 WR RD WR RD D0 to D7
Symbol
Condition -- -- --
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8
-- CL = 100 pF
12
SED1565 Series
(VDD = 1.8 V to 2.7 V, Ta = -40 to 85C ) Rating Units Min Max 0 -- ns 0 -- ns 1000 -- ns 120 -- ns 240 -- ns 120 -- ns 120 -- ns 80 -- ns 30 -- ns -- 280 ns 10 200 ns
Item Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Address hold time RD access time Output disable time
Signal A0 A0 WR RD WR RD D0 to D7
Symbol
Condition -- -- --
tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8
-- CL = 100 pF
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CS1 being "L" (CS2 = "H") and WR and RD being at the "L" level.
q System Bus Read/Write Characteristics 2 (6800 Series MPU)
A0 R/W
tAW6
CS1 (CS2="1")
tAH6
tCYC6 tEWHR, tEWHW
E
tEWLR, tEWLW tDS6
D0 to D7 (Write)
tDS6
tACC6
D0 to D7 (Read)
tOH6
13
SED1565 Series
(VDD = 4.5 V to 5.5 V, Ta = -40 to 85C ) Rating Units Min Max 0 -- ns 0 -- ns 166 -- ns 30 -- ns 10 -- ns -- 70 ns 10 50 ns 70 -- ns 30 -- ns 30 -- ns 30 -- ns (VDD = 2.7 V to 4.5 V, Ta = -40 to 85C ) Rating Units Min Max 0 -- ns 0 -- ns 300 -- ns 40 -- ns 15 -- ns -- 140 ns 10 100 ns 120 -- ns 60 -- ns 60 -- ns 60 -- ns (VDD = 1.8 V to 2.7 V, Ta = -40 to 85C ) Rating Units Min Max 0 -- ns 0 -- ns 1000 -- ns 80 -- ns 30 -- ns -- 280 ns 10 200 ns 240 -- ns 120 -- ns 120 -- ns 120 -- ns
Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Enable L pulse time
Signal A0 A0 D0 to D7
Symbol
Condition -- -- -- CL = 100 pF -- --
Read Write Read Write
E E
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tCCLW tCCLR tCCHW tCCHR
Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Enable L pulse time
Signal A0 A0 D0 to D7
Symbol
Condition -- -- -- CL = 100 pF -- --
Read Write Read Write
E E
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tCCLW tCCLR tCCHW tCCHR
Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse time Enable L pulse time
Signal A0 A0 D0 to D7
Symbol
Condition -- -- -- CL = 100 pF -- --
Read Write Read Write
E E
tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tCCLW tCCLR tCCHW tCCHR
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being "L" (CS2 = "H") and E.
14
SED1565 Series
q Serial Interface
CS1 (CS2="1")
tCSS
tCSH
tSAS
A0
tSAH
tSCYC tSLW
SCL
tSHW tf tSDS
SI
tr tSDH
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
Signal SCL
Symbol
Condition --
A0 SI CS
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
-- -- --
(VDD = 4.5 V to 5.5 V, Ta = -40 to 85C ) Rating Units Min Max 200 -- ns 75 -- ns 75 -- ns 50 -- ns 100 -- ns 50 -- ns 50 -- ns 100 -- ns 100 -- ns (VDD = 2.7 V to 4.5 V, Ta = -40 to 85C ) Rating Units Min Max 250 -- ns 100 -- ns 100 -- ns 150 -- ns 150 -- ns 100 -- ns 100 -- ns 150 -- ns 150 -- ns
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
Signal SCL
Symbol
Condition --
A0 SI CS
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
-- -- --
15
SED1565 Series
(VDD = 1.8 V to 2.7 V, Ta = -40 to 85C ) Rating Units Min Max 400 -- ns 150 -- ns 150 -- ns 250 -- ns 250 -- ns 150 -- ns 150 -- ns 250 -- ns 250 -- ns
Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time
Signal SCL
Symbol
Condition --
A0 SI CS
tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH
-- -- --
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
q Display Control Output Timing
CL (OUT)
tDFR
FR
Item FR delay time
Signal FR
Symbol
Condition CL = 50 pF
tDFR
(VDD = 4.5 V to 5.5 V, Ta = -40 to 85C) Rating Units Min Typ Max -- 10 40 ns (VDD = 2.7 V to 4.5 V, Ta = -40 to 85C) Rating Units Min Typ Max -- 20 80 ns (VDD = 1.8 V to 2.7 V, Ta = -40 to 85C) Rating Units Min Typ Max -- 50 200 ns
Item FR delay time
Signal FR
Symbol
Condition CL = 50 pF
tDFR
Item FR delay time
Signal FR
Symbol
Condition CL = 50 pF
tDFR
*1 Valid only when the master mode is selected. *2 All timing is based on 20% and 80% of VDD.
16
SED1565 Series
q Reset Timing
tRW
RES
tR
Internal status During reset Reset complete
Item FR delay time Reset "L" pulse width
Signal
Symbol
Condition --
RES
tR tRW
(VDD = 4.5 V to 5.5 V, Ta = -40 to 85C) Rating Units Min Typ Max -- -- 0.5 s 0.5 -- -- s (VDD = 2.7 V to 4.5 V, Ta = -40 to 85C) Rating Units Min Typ Max -- -- 1 s 1 -- -- s (VDD = 1.8 V to 2.7 V, Ta = -40 to 85C) Rating Units Min Typ Max -- -- 1.5 s 1.5 -- -- s
Item FR delay time Reset "L" pulse width
Signal
Symbol
Condition --
RES
tR tRW
Item FR delay time Reset "L" pulse width
Signal
Symbol
Condition --
RES
tR tRW
*1 All timing is specified with 20% and 80% of VDD as the standard.
NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) Seiko Epson Corporation 2000 All right reserved. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
ELECTRONIC DEVICES MARKETING DIVISION
IC Marketing & Engineering Group ED International Marketing Department I (Europe, U.S.A) 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042-587-5812 FAX: 042-587-5564 ED International Marketing Department II (ASIA) 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042-587-5814 FAX: 042-587-5110
s Electronic devices information on the Epson WWW server.
http://www.epson.co.jp/device/
First issue February, 1999 Printed in February, 2000 Japan H 17

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